Branch Instruction

br

Operation Font Conventions

Instruction Type B

Format

(bp) br.btype .bwh .ph .dhtarget25 IP_relative_form
 

(bp) br.btype.bwh.ph.dh b1 = target25 call_form, IP_relative_form
 

br.btype.bwh.ph.dh target25 counted_form, IP_relative_form
 

br.ph.dh target25 pseudo-op
 

(bp) br.btype.bwh.ph.dh b2 indirect_form
 

(bp) br.btype.bwh.ph.dh b1 = b2 call_form, indirect_form
 

br.ph.dh b2 pseudo-op

Description

A branch calculation is evaluated, and either a branch is taken, or execution continues with the next sequential instruction. The execution of a branch logically follows the execution of all previous non-branch instructions in the same instruction group. On a taken branch, execution begins at slot 0.

Branches can be either IP-relative, or indirect. For IP-relative branches, the target25 operand, in assembly, specifies a label to branch to. This is encoded in the branch instruction as a signed immediate displacement (imm21) between the target bundle and the bundle containing this instruction (imm21 = target25 - IP >> 4). For indirect branches, the target address is taken from BRb2.

There are two pseudo-ops for unconditional branches. These are encoded like a conditional branch (btype = COND), with the bp field specifying PR 0, and with the bwh hint of sptk.

Basic Branch Types

The branch type determines how the branch condition is calculated and whether the branch has other effects (such as writing a link register). For the basic branch types, the branch condition is simply the value of the specified predicate register (termed the branch predicate).

The basic branch types are:

Read after Write (RAW) and Write after Read (WAR) dependency requirements are slightly different for branch instructions. Changes to BRs, PR s, and PFS by non-branch instructions are visible to a subsequent branch instruction in the same instruction group (i.e., a limited RAW is allowed for these resources). This allows for a low-latency compare-branch sequence, for example. The normal RAW requirements apply to the LC and EC application registers, and the RRBs.

Within an instruction group, a WAR dependency on PR 63 is not allowed if both the reading and writing instructions are branches. For example, a br.wtop or br.wexit may not use PR[63] as its qualifying predicate and PR[63] cannot be the qualifying predicate for any branch preceding a br.wtop or br.wexit in the same instruction group.

For dependency purposes, the loop-type branches effectively always write their associated resources, whether they are taken or not. The cloop type effectively always writes LC. When LC is 0, a cloop branch leaves it unchanged, but hardware may implement this as a re-write of LC with the same value. Similarly, br.ctop and br.cexit effectively always write LC, EC, the RRBs, and PR[63]. br.wtop and br.wexit effectively always write EC, the RRBs, and PR[63].

Values for various branch hint completers are shown as follows: Whether Prediction Strategy hints are shown in bwh completer) Sequential Prefetch Hint (ph) and Branch Cache Deallocation Hint (dh)

 

 

 

 

 

 

 

For details, see Volume 3: Instruction Set Reference of the Intel(R) Itanium(R) Architecture Software Developer's Manual . For the latest updates on the instruction set information, go to the web site.