About Memory EventsAbout Memory EventsThis section summarizes events related to the Itanium(R) processor's memory hierarchy. The memory
hierarchy events are grouped as follows:
L1 Instruction Cache and Prefetch Events
L1 Data Cache Events
L2 Unified Cache Events
L3 Cache Events
An overview of the Itanium 2 processor's three level memory hierarchy and its event monitors is shown in here. The instruction and the data stream work through separate L1 caches. The L1 data cache is a write-through cache. A unified L2 cache serves both the L1 instruction and data caches, and is backed by a large unified L3 cache.
