On systems based on the IA-32 architecture, the FPU status word includes bits that show the floating-point exception state of the processor. The status word parameters describe six exceptions: invalid result, denormalized operand, zero divide, overflow, underflow and inexact precision. These are described in the section, Loss of Precision Errors. When one of the bits is set to 1, it means a past floating-point operation produced that exception type. (Intel Fortran initially clears all status bits. It does not reset the status bits before performing additional floating-point operations after an exception occurs. The status bits accumulate.)
The following table shows the floating-point exception status parameters:
Parameter Name |
Value in Hex |
Description |
|---|---|---|
FPSW$MSW_EM |
#003F |
Status Mask (set all bits to 1) |
FPSW$INVALID |
#0001 |
An invalid result occurred |
FPSW$DENORMAL |
#0002 |
A denormal operand occurred |
FPSW$ZERODIVIDE |
#0004 |
A divide by zero occurred |
FPSW$OVERFLOW |
#0008 |
An overflow occurred |
FPSW$UNDERFLOW |
#0010 |
>An underflow occurred |
FPSW$INEXACT |
#0020 |
Inexact precision occurred |
You can find out which exceptions have occurred by retrieving the status word and comparing it to the exception parameters. For example:
USE IFPORT
INTEGER(2) status
CALL GETSTATUSFPQQ(status)
IF (IAND (status, FPSW$INEXACT) > 0) THEN
WRITE (*, *) "Inexact precision has occurred"
ELSE IF (IAND (status, FPSW$DENORMAL) > 0) THEN
WRITE (*, *) "Denormal occurred"
END IF
To clear the status word flags, call the CLEARSTATUSFPQQ (IA-32 architecture only) routine.
Note
The GETSTAUSFPQQ and CLEARSTATUSFPQQ routines only affect the x87 status register. They do not affect the MXCSR register (the control and status register for the Intel® SSE and Intel® SSE2 instructions).